US4805131A - BCD adder circuit - Google Patents US4805131A - BCD adder circuit - Google Patents BCD adder circuit Info Publication number US4805131A US4805131A US07072161 US7216187A US4805131A US 4805131 A US4805131 A US 4805131A US 07072161 US07072161 US 07072161 US 7216187 A US7216187 A US 7216187A US 4805131 A US4805131 A US 4805131A Authority US Grant status Grant Patent type Prior art keywords vector bcd carry intermediate sum Prior art date 1987-07-09 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Expired - Lifetime Application number US07072161 Inventor Matthew J.
Adiletta Virginia C. Lamere Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Hewlett Packard Development Co LP Original Assignee Digital Equipment Corp Priority date (The priority date is an assumption and is not a legal conclusion.
Would be 17 (1 0111). Implement such a BCD adder using a 4-bit adder and appropriate control circuitry in a VHDL code. Assume that the two BCD.
Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 1987-07-09 Filing date 1987-07-09 Publication date 1989-02-14 Grant date 1989-02-14 Links. Images. Classifications. G— PHYSICS. G06— COMPUTING; CALCULATING; COUNTING. G06F— ELECTRIC DIGITAL DATA PROCESSING. G06F7/00— Methods or arrangements for processing data by operating upon the order or content of the data handled.
G06F7/38— Methods or arrangements for performing computations using exclusively denominational number representation, e.g. Using binary, ternary, decimal representation. G06F7/48— Methods or arrangements for performing computations using exclusively denominational number representation, e.g. Using binary, ternary, decimal representation using non-contact-making devices, e.g. Tube, solid state device; using unspecified devices. G06F7/491— Computations with decimal numbers radix 12 or 20.
G06F7/492— Computations with decimal numbers radix 12 or 20. Using a binary weighted representation within each denomination. G06F7/493— Computations with decimal numbers radix 12 or 20. Using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor.
A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs. BACKGROUND OF THE INVENTION The present invention relates to a binary coded decimal (BCD) adder circuit.
Binary coded decimal numbers are used to represent decimal numbers in a form readily understood by both man (decimal) and computer (binary). There are sixteen possible bit combinations using four binary bits, but only ten are valid BCD digits. Therefore, when two BCD digits are added and the sum digit exceeds nine, that sum digit must be adjusted to a valid BCD digit. This is generally done by adding the constant 0110 2 (6 10) to the sum. Traditionally, BCD adder circuits have used logic to detect whether a BCD sum should be adjusted after the addition has been completed.
For example, whenever the unadjusted sum of two BCD digits produced a carry-out (i.e., when the sum exceeds fifteen), the sum was corrected by adding 0110 2. Also, an adjustment was needed whenever bit positions 8 and 4 of the BCD sum were both one's (values 12 10 -15 10) or when bit positions 8 and 2 were both one's (values 10 10 and 11 10). Traditional BCD adder circuits, for example, such as the circuit 10 shown in FIG. 1, use standard four-bit binary adders to add two BCD digits to produce an intermediate sum (Z 8,Z 4, Z 2, Z 1).
The adder circuit also includes correction logic for each intermediate sum digit greater than nine. In the circuit shown in FIG.
1, a first four-bit operand, bits a(0) 8 to a(0) 1, and a second four-bit operand, bits b(0) 8 to b(0) 1, are input in parallel to full adder 15 along with the C in or carry-in bit. The output from full adder 15 includes a four-bit sum vector Z (Z 8 to Z 1) and a carry-out C out. If C out is '1' or if either Z 8 and Z 4 are both '1' (AND gate 20) or Z 8 and Z 2 are both '1' (AND gate 25), the BCD adder circuit 10 produces a C(0) out BCD carry from OR gate 30 and the sum vector Z is corrected by adding a value of '0110 2 ' to the sum vector Z. When C(0) out is a '1' the B input of second full adder 35 receives a '0110 2 ' value while the sum vector Z is received at the A input of full adder 35. The output of full adder 35, S(0) 8 to S(0) 1, is the adjusted BCD sum of the original two operands. As is apparent, traditional BCD adder circuits of present advanced VLSI technology, utilizing a carry-propagate full adder circuit such as 10, have a great amount of delay associated with them due to the display associated with propagation of carries through the adder circuitry (15, 35) and the delay associated with the correction circuitry (gates 20, 25, and 30).
The delay associated with traditional carry-propagate full adder circuits, such as 15 and 35, is equal to: Delay=log.sub.2 (operand width, i.e., number of bits per operand). Therefore, the delay associated with adders 10 and 35 is equal to log 2 (4), or two units of delay.
The delay associated with the correction circuitry is equal to two units of delay since there are two gate levels to the circuit for a total delay of four units for the adder of FIG. As the width of the operand increases, for example, when two 32-bit operands are to be added, the associated delay also increases. A traditional BCD adder circuit would require eight stages of carry-propagate full adders plus associated correction circuitry to perform the addition of two 32-bit operands, and thus, the associated delay could be as high as thirty-two units for this adder circuit. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a BCD adder circuit which reduces the time required to perform a BCD addition of two numbers. Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
The BCD adder circuit of claim 1 wherein said adder means includes a plurality of parallel full adder circuits, each of said full adder circuits being connected to receive as inputs a unique set of successive bits of said first operand, a unique and corresponding set of successive bits of said second operand, and a corresponding portion of said precorrection factor, said plurality of full adder circuits each providing as an output a unique set of successive bits of said intermediate sum vector, and a unique set of successive bits of said intermediate carry vector. The BCD adder circuit of claim 2 wherein said unique set of successive bits of said first operand is equal to four bits, said unique set of successive bits of said second operand is equal to four bits, and wherein each of said full adder circuits is comprised of four parallel 1-bit full adders, each of said full adders receiving as inputs four bits of said first operand, four bits of said second operand and four bits of said BCD precorrection factor and outputting four bits of said intermediate sum vector and four bits of said intermediate carry vector. Modifying said propagate vector according to said final carry vector to form said BCD sum if said intermediate and final carry vectors do not have said predetermined relationship.
10’s Complement Subtraction The 10’s complement can be used to perform subtraction by adding the minuend to the 10’s complement of the subtrahend and dropping the carry. This is illustrated in following examples. From the above examples we can summarize steps for 9’s complement BCD subtraction as follows:.
Find the 9’s complement of a negative number. Add two numbers using BCD addition. If carry is generated add carry to the result otherwise find the 9’s complement of the result. 3.34 shows the logic diagram of the circuit to implement above mentioned steps to perform BCD subtraction using 9’s complement method.
As shown in the Fig. 3.34, first binary adder finds the 9’s complement of the negative number. It does this by inverting each bit of BCD number and adding 10 (1 0 1 0 2) to it. Let us find the 9’s complement of 2 Next two 4-bit adders perform the BCD addition. The last adder finds the 9’s complement of the result if carry is not generated after BCD addition otherwise it adds carry in the result. 3.34 on previous page).
From the above examples we can summarize steps for 10’s complement BCD subtraction as follows. Find the 10’s complement of a negative number. Add two numbers using BCD addition.
If carry is not generated find the 10’s complement of the result. 3.35 shows the logic diagram of the circuit to implement above mentioned steps to perform BCD subtraction using 10’s complement method. As shown in the Fig. 3.35, first binary adder finds the 10’s complement of the negative number (9’s complement + 1).
Next two 4-bit binary adders perform the BCD addition. Finally, last 4-bit binary adder finds the 10’s complement of the number if carry is not generated after BCD addition.